1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to an external connection terminal for preventing electrostatic discharge damage.
2. Description of Related Art
Recently the use of COG (Chip On Glass) packaging, which excels in high density packaging, is rapidly spreading. In a COG package, gold bumps or solder bumps for packaging on a substrate are formed directly on the semiconductor device chip (hereafter called a “device chip”), and the bumps on the device chip are bonded with a metal wiring printed on the glass or ceramic substrate to be connected with external equipment. With such a COG packing, since the packaging area for the substrate is the same size as the device chip, extremely high density packaging is possible.
Also in the case of a semiconductor integrated circuit, represented by the so called “system LSI”, such as a microcontroller and an LSI for communication, the voltage supplied from an external power supply cannot be used for operation of the semiconductor integrated circuit as is, but is used for internal operation after performing voltage adjustment. Voltage adjustment is performed by amplifying the reference voltage generated in the semiconductor integrated circuit by an operational amplifier (hereinafter called OP-amp) using the forward voltage of the diode. This voltage adjustment is performed to prevent abnormal functioning of the semiconductor integrated circuit which occurs when the supply voltage from the external power supply is unstable.
Also among these semiconductor circuits, semiconductor circuits which are particularly sensitive to reference voltage have fuse terminals for output voltage adjustment. Transistors constituting the OP-amp may have some dispersion of threshold voltage depending on the wafer or the chip. If threshold voltage changes, the amplification characteristics of the OP-amp also changes. When the output voltage of the OP-amp deviates from a desired value, the resistance value of the feedback resistance of the OP-amp is adjusted by blowing out a specific fuse, so that the output voltage becomes a predetermined value.
Today reference voltages are dropping since the driving voltages of semiconductor integrated circuits are decreasing, so the amplification characteristics of the OP-amp are becoming more easily influenced by the dispersion of threshold voltage. As a result, there is a tendency that the use of semiconductor integrated circuits, which have the above mentioned fuses, are increasing.
An example of the amplification circuit which has fuses will be described with reference to FIG. 9.
FIG. 9 (A) shows an example of a general amplification circuit using an OP-amp. The internally generated reference voltage (hereafter called “reference voltage”) V0 generated in the semiconductor integrated circuit is amplified by the OP-amp 200, and is output as the reference voltage for device driving (hereafter also called “output voltage”) V0′, which is used for driving the semiconductor integrated circuit, for example. The output voltage V0′ of the OP-amp 200 is determined by the resistance value Ri of the resistance element 202 and the resistance value Rf on the feedback resistance 204. The resistance element 202 is comprised of a fixed resistance element of which the resistance value does not change, and the feedback resistance 204 is comprised of a variable resistance element. If the output voltage V0′ of the OP-amp deviates from a desired value, the output voltage V0′ is adjusted by changing the resistance value Rf of the feedback resistance 204.
FIG. 9 (B) shows a circuit for resistance value adjustment of the feedback resistance 204. In the feedback resistance 204, a plurality of resistance elements (eight in this case) are connected in series. The circuit for resistance value adjustment, where PMOS is integrated, is connected to each of the plurality of resistance elements in parallel. This circuit for resistance value adjustment is connected with a reference voltage (VDD) via the inverter and the pull-up resistance elements 210a–210c, and is also connected to the ground (GND) potential via the fuses 206a–206c. The fuses 206a–206c have protective resistance elements 208a–208c respectively, for protecting the circuit for resistance value adjustment when fuses are blown out. When the fuses 206a–206c are blown out, the high level (VDD) or the low level (GND) of the signal of the voltage supplied to the PMOS changes, and the route where the current of the adjustment circuit runs changes, and the current does not run through a part of the eight resistance elements connected in series, so the resistance value Rf of the feedback resistance changes.
FIG. 10 shows a schematic of a general COG package. The device chip 230 comprises fuse terminals and chip terminals which have a protective circuit. On the surface of the device chip 230, bumps 232 of the chip terminals are arranged in a line along the edge, and a plurality of bumps 234 of the fuse terminals, which are lined up in a line, are disposed in the inner area of the bumps 232 of the chip terminals.
FIG. 11 shows an example of the protective circuit used for the chip terminal. The protective circuit is disposed between the chip terminal 212 and the internal circuit 213. Between the chip terminal 212 and the resistance element 218, a protective diode 214 connected to the reference voltage (VDD) and a protective diode 216 connected to the ground potential (GND) are disposed. The resistance element 218 is connected to the internal circuit 213 via the inverter 220. This protective circuit protects the internal circuit 213 from electrostatic discharge damage by discharging an electrostatic surge which enters the chip terminal to VDD via the protective diode 214 or to GND via the protective diode 216.
In the case of the COG package, a fuse terminal for connecting with external equipment is disposed also in a circuit which has a fuse. In a conventional resin sealing type package which has been frequently used, the fuse terminal is not led out as an external terminal to be connected with the external power supply, but is sealed in the resin. Therefore the fuse terminal does not have the protective circuit which the chip terminal has, since the fuse terminal is not exposed to static electricity.
Also in a TAB (Tape Automated Bonding) type package, it has been proposed to increase the height of bump electrodes at the outer side so as to suppress the thermal expansion of the inner leads to be connected to the bump electrodes at the inner side during thermo-compression bonding (see Japanese Patent Application Laid-Open No. 5-218130). In Japanese Patent Application Laid-Open No. 5-218130, the heights of adjacent bump electrodes are adjusted by adjusting the plating conditions, however the detailed method is not disclosed.
As another example of having bump electrodes with different heights is a method of preventing the contact of adjacent bump electrodes due to the thermal cycle by shifting the heights of the bonding face of the bump electrodes between the external substrate and the device chip (see Japanese Patent Application Laid-Open 5-343407). In Japanese Patent Application Laid-Open 5-343407, the heights of the bumps of the device chip and the external substrate to be connected are formed to be high in one and low in the other. Also the heights of the adjacent bumps on the device chip and the external substrate are formed to be different, so the heights of the bonding faces of the adjacent bumps are different, and contact between the bump electrodes is prevented.
In a conventional resin sealing type package, the fuse terminal is not led outside, so it is not exposed to electrostatic discharge damage during packaging, and does not require the protective circuit. In the COG package, bumps for connection are formed for the fuse terminal as well as the other chip terminals, so the fuse terminal is led out as a terminal to be connected to the outside. Therefore in the device chip having a fuse, electrostatic discharge damage by a charged external substrate tends to occur when it is connected with the external substrate.
As an example, FIG. 12 shows a schematic of the electrostatic discharge phenomena in the packaging step of the COG package.
On the external substrate 240 for external equipment connection, a plurality of device chips are sequentially connected. In FIG. 12, the device chip 244 is already connected to the external substrate 240. To this external substrate 240, the device chip 230 comprising a circuit, which has the fuse shown in FIG. 10, is connected. The external substrate 240 is made of glass or ceramic, so it is very easily charged. When the device chip 230 is connected to the external substrate 240, electrostatic discharge occurs in the fuse terminal 234 or the chip terminal 232. If discharge occurs to the chip terminal 232, electrostatic discharge damage does not occur since the chip terminal 232 has a protective circuit. If the electrostatic discharge 246 occurs to the fuse terminal 234, however, electrostatic discharge damage occurs. In other words, the fuse in the circuit of the semiconductor integrated circuit is blown out, and the resistance value, which has been adjusted to a desired resistance value, changes.
If a protective circuit similar to that of the chip circuit is included in the fuse terminal, the occupied area of the chip increases. This increases the chip size, which also increases chip cost. Also a general resin sealing type chip does not have a protective circuit in the fuse terminal, so it cannot be used for a COG type chip as is. Therefore it is necessary to develop a new device chip where a protective circuit is disposed in a fuse terminal.
With the foregoing in view, it is an object of the present invention to provide a semiconductor device for protecting from electrostatic discharge damage while suppressing the increase in the chip area in a packaging system for a COG package where a fuse terminal is directly connected to an external substrate for connecting with external equipment.